A conventional level converter of this kind is known as a circuit for converting signals with the amplitude of a low voltage power supply VDD to signals with the amplitude of a high voltage power supply VDDQ as disclosed in “Super LSI Memory” written by Ito Kiyoo, page 71, 1996, published by Baifukan (this level converter will be referred to as prior art 1 hereinafter). In order to apply the level converter of prior art 1 to operation on lower voltage as low voltage power supply VDD, a circuit was configured to convert input signals to those with the amplitude of a boosted voltage and further converts the signals to those with the voltage amplitude level of high voltage power supply VDDQ, which was disclosed in Kokai (Japanese Unexamined Patent Publication) No. Hei 11-27137 (No. 27137 of 1999) (This will be referred to as prior art 2 hereinafter).
FIG. 22 is a circuit diagram representing the level converter of prior art 2. This level converter is comprised of a voltage-up circuit VUC that boots the voltage of signals with the amplitude of a low supply voltage VDL, which have been input from an inside-chip circuit CB using a VDL power supply as its operating power supply, and a level converter LS2201 that is the same as the level converter of prior art 1 and converts the voltage-boosted input signals to signals with the amplitude of high supply voltage VDH. The level converter LS2201 of prior art 1 is a so-called CMOS static type and configured with p-channel MOSFETs (hereinafter referred to as PMOS transistors) P2201 and P2202 and n-channel MOSFETs (hereinafter referred to as NMOS transistors) N2201 and N2202.
Output from the voltage-up circuit VUC is received by the gates of a pair of differential input NMOS transistors N2201 and N2202 and converted to signals S2002 with the output amplitude of high supply voltage VDH level. The PMOS transistors P2201 and P2202 make loads to the differential input NMOS transistors N2201 and N2202 and they are cross connected such that the gate of one PMOS transistor is connected to the drain of the other PMOS transistor.
Higher voltage than input level VDL is applied to the gates of the NMOS transistors N2201 and N2202 and its effect is increasing the drive power of both the NMOS transistors N2201 and N2202. Therefore, the circuit shown in FIG. 22 enables operation on lower voltage VDL than in a case that the level converter of prior art 1 solely functions.
The voltage-up circuit disclosed in prior art 2 is shown in FIG. 23. This voltage-up circuit outputs a 2×VDL level, but can do temporarily. That is, a maximum of VDL level is only applied to the gates of the PMOS transistors P2301 and P2302, and therefore of the terminals of PMOS transistors P2301 and P2304 to which the capacitors C2301 and C2302 are connected change from the drain state to the source state. Consequently, the 2×VDL level cannot remain constant and drops to a voltage equaling the power supply voltage VDL plus the PMOS transistor threshold voltage.
Accordingly, if the power supply voltage VDL is, for example, as low as 1 V or below, it is not enough to drive the level converter of prior art 1. Voltage to be applied to some of the MOS transistors used as the components of the circuit shown in FIG. 23 will reach a maximum of 2×VDL for a moment. Thus, low voltage tolerant MOS transistor devices produced by thin oxide film deposition are difficult to use and it is necessary to fabricate an integrated circuit with high voltage tolerant MOS transistor devices produced by thick oxide film deposition. This may result in difficulty in increasing the operating speed of the IC.
A single voltage-up circuit example was disclosed in Kokai (Japanese Unexamined Patent Publication) No. Sho 63-69455 (No. 69455 of 1988). This circuit example gives a 2×VCC−VT level (VCC: power supply voltage, VT: threshold voltage of an NMOS transistor). Furthermore, another voltage-up circuit configuration was disclosed in Kokai (Japanese Unexamined Patent Publication) No. Hei 3-273594 (No. 273594 of 1991). This circuit gives a 2×VL level by using a voltage-up circuit giving 2×VL−VT (VL: low voltage) and a voltage tripler.
Even if the former disclosed voltage-up circuit that increases voltage to a 2×VCC−VT level is used as the voltage-up circuit in the circuit implementation of prior art 2, very low power supply voltage VDL may cause the level converter of prior art 1 to be inoperative.
When the voltage-up circuit configuration giving a 2×VL level disclosed in Kokai No. Hei 3-273594 is used, MOS transistors produced by thicker oxide film deposition must be used to implement the voltage tripler. Due to the increased number of the MOS transistors, increase of mounting area is inevitable and results in high cost.
A single level converter example was disclosed in Kokai (Japanese Unexamined Patent Publication) No. Sho 63-299409 (No. 299409 of 1988) (This will be referred to as prior art 3 hereinafter). This level converter carries out level conversion, taking advantage of a signal with its level shifted from the level of an input signal. For level shifting, a resistor and MOS transistors are used. FIG. 24 shows the level converter disclosed in prior art 3. This circuit carries out level conversion, taking advantage of potential down to which voltage is dropped by a resistor R2401. Consequently, for example, if voltage VIN at the gate pin of an NMOS transistor N2405 is equal to voltage VDD at the gate pin of an NMOS transistor N2404, that is, VIN=VDD, current always flows from a high potential pin VDDQ to a low potential pin VSSQ. This is not desirable from the point of view of reducing power consumption that is very important for a low-voltage circuit.
While the previous implementation examples of level converter and voltage-up circuit were discussed above, another problem of the level converter should be considered as will be described below. This problem is a leakage current that occurs in a logic circuit driven by high voltage power supply VDDQ when a circuit block that uses the low voltage power supply VDD as its power supply, connected to the level converter, is powered off. As a protection circuit for preventing this leakage current, a level converter with fixed output in which output to the high voltage side is fixed to the voltage of high voltage power supply VDDQ by external signal input was disclosed in Kokai (Japanese Unexamined Patent Publication) No. Hei 11-195975 (No. 195975 of 1999). This circuit is effective, but it is ideal that a leak protection circuit prevents leaks by autonomous control dispensing with external control signals and such circuit is desirable in view of simplifying design.
In the light of recent trend of IC technology toward reducing power consumption, lowering the power supply voltage of low-voltage logic circuits down to below 1 V is actively pursued. On the other hand, however, as high voltage as 3.3 V or 2.5 V is still required for components driven by high voltage, such as, typically, I/O circuits and word-line driving circuits of a dynamic random access memory (DRAM). Thus, attention must be paid to the following two points.
1. Difference between the power supply voltage of low-voltage logic circuits and that of high-voltage logic circuits becomes great.
2. If the level (for example, 0.7 V) of the low-voltage-side circuit operation (low voltage power supply VDD) becomes as low as the threshold voltage (VTH, for example, 0.7 V) of high-voltage-side circuit operation (high voltage power supply VDDQ, for example, 3.3 V), the low voltage power supply VDD level is too low to drive the level converter.
These problems place limitations on the operation of previous level converters. Because the voltage-up circuit disclosed in Kokai No. Hei 11-27137 gives a 2×VDD level, but does only for a moment as described above, it may be difficult to operate the level converter when the low voltage power supply VDD is very low below 1 V. In addition, voltage to be applied to low-voltage circuits reaches a maximum of 2×VDD, and therefore, MOS transistors of low-voltage circuits must be produced by thick oxide film deposition, consequently bottlenecking high-speed operation.
In connection with the voltage-up circuit, the previous implementation example of level converter (Kokai No. Hei 3-273594) outputs a 2×VDD level. However, the voltage tripler is added to this implementation to give a 2×VDD level and this posed the problems: MOS transistors produced by thicker oxide film deposition are required; the increased number of components; and, consequently, increase of mounting area.
As discussed in Kokai No. Hei 11-195975, when the low-voltage-side power supply is off, a leakage current occurs in the following stage of high-voltage-side circuits; this leakage current problem will be described in detail in a later section regarding the preferred embodiments of the invention. According to the above Kokai publication, external control signals are used to inhibit the leakage current. However, if the level converter can be configured to autonomously control the leakage current, simpler circuit design and reduced cost can be achieved.
An object of the present invention is to provide a semiconductor device comprising a high-voltage-driven circuit operating on a high voltage of power supply, a low-voltage-driven circuit operating on a low voltage of power supply, and a level converter for converting the signal level of the Low-voltage-driven circuit to the signal level of the high-voltage-driven circuit, wherein the level converter operates even when the low voltage power supply supplies a voltage of below 1 V.
Another object of the present invention is to provide a semiconductor device further including a circuit for preventing a leakage current from occurring in the level converter when the above low-voltage-driven circuit is placed in sleep mode.